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1 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 mx25u8035e/mx25u1635e/ mx25u3235e datasheet
2 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 contents features .................................................................................................................................................................. 6 general description ......................................................................................................................................... 8 table 1. additional feature comparison ............................................................................................................... 9 pin configurations ........................................................................................................................................... 10 pin description .................................................................................................................................................... 10 block diagram ..................................................................................................................................................... 1 1 data protection .................................................................................................................................................. 12 table 2. protected area sizes ............................................................................................................................. 13 table 3. 4k-bit secured otp defnition ............................................................................................................... 13 memory organization ............................................................................................................................................... 14 table 4-1. memory organization (8mb) .............................................................................................................. 14 table 4-2. memory organization (16mb) ............................................................................................................ 15 table 4-3. memory organization (32mb) ............................................................................................................ 16 device operation ................................................................................................................................................ 18 figure 1. serial modes supported ....................................................................................................................... 18 quad peripheral interface (qpi) read mode ...................................................................................................... 19 figure 2. enable qpi sequence (command 35h) .............................................................................................. 19 quad peripheral interface (qpi) operation .......................................................................................................... 19 figure 3. high-speed read sequence (qpi) (command 0bh) .......................................................................... 19 figure 4. reset qpi mode (command f5h) ....................................................................................................... 20 figure 5. fast qpi read mode (fastrdq) (command ebh) ........................................................................... 20 command description ....................................................................................................................................... 21 table 5. command set ........................................................................................................................................ 21 (1) write enable (wren) .................................................................................................................................... 23 (2) write disable (wrdi) ..................................................................................................................................... 23 (3) read identifcation (rdid) ............................................................................................................................. 23 (4) read status register (rdsr) ....................................................................................................................... 23 program/ erase fow with read array data ........................................................................................................... 24 program/ erase fow without read array data (read regpfail/regefail fag) ............................................... 25 wrsr fow .......................................................................................................................................................... 26 (5) write status register (wrsr) ....................................................................................................................... 28 table 6. protection modes ................................................................................................................................... 28 (6) read data bytes (read) .............................................................................................................................. 29 (7) read data bytes at higher speed (fast_read) ........................................................................................ 29 (8) 2 x i/o read mode (2read) ......................................................................................................................... 29 (9) 4 x i/o read mode (4read) ......................................................................................................................... 30 (10) burst read ................................................................................................................................................... 31
3 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (11) performance enhance mode ....................................................................................................................... 32 (12) performance enhance mode reset (ffh) ................................................................................................... 32 (13) sector erase (se) ........................................................................................................................................ 32 (14) block erase (be32k) ................................................................................................................................... 33 (15) block erase (be) .......................................................................................................................................... 33 (16) chip erase (ce) ........................................................................................................................................... 33 (17) page program (pp) ...................................................................................................................................... 34 (18) 4 x i/o page program (4pp) ........................................................................................................................ 34 (19) deep power-down (dp) ............................................................................................................................... 35 (20) release from deep power-down (rdp), read electronic signature (res) ............................................... 35 (21) read electronic manufacturer id & device id (rems) ............................................................................... 36 (22) qpi id read (qpiid) ................................................................................................................................... 36 table 7. id defnitions ........................................................................................................................................ 36 (23) enter secured otp (enso) ........................................................................................................................ 37 (24) exit secured otp (exso) ........................................................................................................................... 37 (25) read security register (rdscur) ............................................................................................................. 37 table 8. security register defnition ................................................................................................................... 38 (26) write security register (wrscur) ............................................................................................................. 38 (27) write protection selection (wpsel) ............................................................................................................ 38 wpsel flow ....................................................................................................................................................... 39 (28) single block lock/unlock protection (sblk/sbulk) .................................................................................. 40 block lock flow .................................................................................................................................................. 40 block unlock flow ............................................................................................................................................... 41 (29) read block lock status (rdblock) .......................................................................................................... 42 (30) gang block lock/unlock (gblk/gbulk) .................................................................................................... 42 (31) read dmc mode (rddmc) ........................................................................................................................ 42 (32) program/ erase suspend/ resume ............................................................................................................. 42 (32-1) erase suspend ......................................................................................................................................... 43 (32-2) program suspend ..................................................................................................................................... 43 (33) write-resume .............................................................................................................................................. 44 (34) no operation (nop) .................................................................................................................................... 44 (35) software reset (reset-enable (rsten) and reset (rst)) ........................................................................ 44 (36) reset quad i/o (rstqio) ........................................................................................................................... 45 power-on state ................................................................................................................................................... 46 electrical specifications .............................................................................................................................. 47 absolute maximum ratings ...................................................................................................................... 47 figure 6. maximum negative overshoot waveform ............................................................................................ 47 capacitance ta = 25c, f = 1.0 mhz .............................................................................................................. 47 figure 7. maximum positive overshoot waveform ............................................................................................. 47 figure 8. input test waveforms and measurement level ............................................................... 48
4 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 9. output loading ............................................................................................................................ 48 table 9. dc characteristics (temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v) ................................. 49 table 10. ac characteristics (temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v) .............................. 50 timing analysis ........................................................................................................................................................ 51 figure 10. serial input timing ............................................................................................................................. 51 figure 11. output timing ..................................................................................................................................... 51 figure 12. wp# setup timing and hold timing during wrsr when srwd=1 .................................................. 52 figure 13-1. write enable (wren) sequence (command 06) (spi mode) ........................................................ 52 figure 13-2. write enable (wren) sequence (command 06) (qpi mode) ....................................................... 52 figure 14-1. write disable (wrdi) sequence (command 04) (spi mode) ........................................................ 53 figure 14-2. write disable (wrdi) sequence (command 04) (qpi mode) ........................................................ 53 figure 15. read identifcation (rdid) sequence (command 9f) (spi mode only) ............................................ 53 figure 16-1. read status register (rdsr) sequence (command 05) (spi mode) ........................................... 54 figure 16-2. read status register (rdsr) sequence (command 05) (qpi mode) .......................................... 54 figure 17-1. write status register (wrsr) sequence (command 01) (spi mode) ......................................... 54 figure 17-2. write status register (wrsr) sequence (command 01) (qpi mode) ......................................... 55 figure 18. read data bytes (read) sequence (command 03) (spi mode only) (33mhz) .............................. 55 figure 19-1. read at higher speed (fast_read) sequence (command 0b) (spi mode) (104mhz) ............ 56 figure 19-2. read at higher speed (fast_read) sequence (command 0b) (qpi mode) (84mhz) .............. 56 figure 20. 2 x i/o read mode sequence (command bb) (spi mode only) (84mhz) ........................................ 57 figure 21. 4 x i/o read mode sequence (command eb) (spi mode) (104mhz) .............................................. 57 figure 22-1. 4 x i/o read enhance performance mode sequence (command eb) (spi mode) (104mhz) ....... 58 figure 22-2. 4 x i/o read enhance performance mode sequence (command eb) (qpi mode) (104mhz) ...... 59 figure 23-1. page program (pp) sequence (command 02) (spi mode) .......................................................... 59 figure 23-2. page program (pp) sequence (command 02) (qpi mode) .......................................................... 60 figure 24. 4 x i/o page program (4pp) sequence (command 38) (spi mode only) ........................................ 60 figure 25-1. sector erase (se) sequence (command 20) (spi mode) ............................................................. 61 figure 25-2. sector erase (se) sequence (command 20) (qpi mode) ............................................................ 61 figure 26-1. block erase 32kb (be32k) sequence (command 52) (spi mode) .............................................. 61 figure 26-2. block erase 32kb (be32k) sequence (command 52) (qpi mode) .............................................. 61 figure 27-1. block erase (be) sequence (command d8) (spi mode) .............................................................. 62 figure 27-2. block erase (be) sequence (command d8) (qpi mode) ............................................................. 62 figure 28-1. chip erase (ce) sequence (command 60 or c7) (spi mode) ...................................................... 62 figure 28-2. chip erase (ce) sequence (command 60 or c7) (qpi mode) ..................................................... 62 figure 29-1. deep power-down (dp) sequence (command b9) (spi mode) ................................................... 63 figure 29-2. deep power-down (dp) sequence (command b9) (qpi mode) ................................................... 63 figure 30-1. release from deep power-down and read electronic signature (res) sequence (command ab) (spi mode) .......................................................................................................................................................... 63 figure 30-2. release from deep power-down and read electronic signature (res) sequence (command ab) (qpi mode) .......................................................................................................................................................... 64
5 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 31-1. release from deep power-down (rdp) sequence (command ab) (spi mode) .......................... 64 figure 31-2. release from deep power-down (rdp) sequence (command ab) (qpi mode) .......................... 64 figure 32. read electronic manufacturer & device id (rems) sequence (command 90) (spi mode only) .... 65 figure 33. word read quad i/o instruction sequence (initial word read quad i/o instruction or previous p4=1) (spi mode only) (84mhz) .................................................................................................................................... 66 figure 34. performance enhance mode reset for fast read quad i/o (spi and qpi mode) ........................... 66 figure 35-1. reset sequence (spi mode) .......................................................................................................... 67 figure 35-2. reset sequence (qpi mode) .......................................................................................................... 67 figure 36. enable quad i/o sequence ............................................................................................................... 67 figure 37-1. suspend to read latency ............................................................................................................... 68 figure 37-2. resume to read latency ............................................................................................................... 68 figure 37-3. resume to suspend latency .......................................................................................................... 68 figure 38. software reset recovery .................................................................................................................. 68 figure 39. power-up timing ................................................................................................................................ 69 table 11. power-up timing and vwi threshold .................................................................................................. 69 initial delivery state .................................................................................................................................. 69 operating conditions ....................................................................................................................................... 70 figure 40. ac timing at device power-up .......................................................................................................... 70 figure 41. power-down sequence ..................................................................................................................... 71 erase and programming performance .................................................................................................... 72 latch-up characteristics .............................................................................................................................. 72 ordering information ...................................................................................................................................... 73 part name description ..................................................................................................................................... 74 package information ........................................................................................................................................ 75 revision history ................................................................................................................................................. 79
6 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 8m-bit [x 1/x 2/x 4] 1.8v cmos mxsmio tm (serial multi i/o) flash memory 16m-bit [x 1/x 2/x 4] 1.8v cmos mxsmio tm (serial multi i/o) flash memory 32m-bit [x 1/x 2/x 4] 1.8v cmos mxsmio tm (serial multi i/o) flash memory features general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 8m:8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two i/o read mode) structure or 2,097,152 x 4 bits (four i/ o read mode) structure 16m:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two i/o read mode) structure or 4,194,304 x 4 bits (four i/o read mode) structure 32m: 32,554,432 x 1 bit structure or 16,777,216 x 2 bits (two i/o read mode) structure or 8,388,608 x 4 bits (four i/o read mode) structure ? equal sectors with 4k byte each, or equal blocks with 32k byte each or equal blocks with 64k byte each - any block can be erased individually ? single power supply operation - 1.65 to 2.0 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v ? low vcc write inhibit is from 1.0v to 1.4v performance ? high performance - fast read for spi mode - 1 i/o: 104mhz with 8 dummy cycles - 2 i/o: 84mhz with 4 dummy cycles, equivalent to 168mhz - 4 i/o: 104mhz with 6 dummy cycles, equivalent to 416mhz - fast read for qpi mode - 4 i/o: 84mhz with 4 dummy cycles, equivalent to 336mhz - 4 i/o: 104mhz with 6 dummy cycles, equivalent to 416mhz - fast program time: 1.2ms(typ.) and 3ms(max.)/page (256-byte per page) - byte program time: 8us (typical) - 8/16/32/64 byte wrap-around burst read mode - fast erase time: 42ms (typ.)/sector (4k-byte per sector); 230ms(typ.) /block (32k-byte per block); 450ms(typ.) / block (64k-byte per block); 5s(typ.) /chip for 8m ; 9s(typ.) /chip for 16m ; 18s(typ.) /chip for 32m ? low power consumption - low active read current: 20ma(max.) at 104mhz, 15ma(max.) at 84mhz - low active erase/programming current: 20ma (typ.) - standby current: 30ua (typ.) ? deep power down: 5ua(typ.) ? typical 100,000 erase/program cycles ? 10 years data retention software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 status bit defnes the size of the area to be software protection against program and erase instructions - additional 4k-bit secured otp for unique identifer
7 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 * advanced information ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector or block - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) ? status register feature ? command reset ? program/erase suspend ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems command for 1-byte manufacturer id and 1-byte device id hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o read mode ? sio3 - serial input & output for 4 x i/o read mode ? package - 8mb (mx25u8035e) - 8-pin sop (150mil) * - 8-pin sop (200mil) * - 8-land wson (6x5mm) * - 8-land uson (4x4mm) * - 16mb (mx25u1635e) - 8-pin sop (150mil) * - 8-pin sop (200mil) * - 8-land wson (6x5mm) * - 8-land uson (4x4mm) * - 32mb (mx25u3235e) - 8-pin sop (200mil) - 8-land wson (6x5mm) - all pb-free devices are rohs compliant
8 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 general description the mx25u8035e are 8,388,608 bit serial flash memory, which is confgured as 1,048,576 x 8 internally. when it is in two or four i/o read mode, the structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. the mx25u1635e are 16,777,216 bit serial flash memory, which is confgured as 2,097,152 x 8 internally. when it is in two or four i/ o read mode, the structure becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. the mx25u3235e are 32,554,432 bit serial flash memory, which is confgured as 4,194,304 x 8 internally. when it is in two or four i/o read mode, the structure becomes 16,777,216 bits x 2 or 8,388,608 bits x 4. mx25u8035e/mx25u1635e/mx25u3235e feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single i/o mode. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits input and data output. when it is in four i/o read mode, the si pin, so pin and wp# pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data output. the mx25u8035e/mx25u1635e/mx25u3235e mxsmio tm (serial multi i/o) provides sequential read operation on whole chip. after program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specifed page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4k-byte), block (32k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and cs# is high, it is put in standby mode and typically draws 30ua dc current. the mx25u8035e/mx25u1635e/mx25u3235e utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.
9 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 table 1. additional feature comparison additional features part name protection and security read performance spi qpi flexible block protection (bp0-bp3) 4k-bit security otp 1 i/o (104 mhz) 2 i/o (84 mhz) 4 i/o (84 mhz) 4 i/o (104 mhz) 4 i/o (84 mhz) 4 i/o (104 mhz) mx25u8035e v v v v v v v v mx25u1635e v v v v v v v v mx25u3235e v v v v v v v v additional features part name identifer res (command: ab hex) rems (command: 90 hex) rdid (command: 9f hex) qpiid (command: af hex) mx25u8035e 34 (hex) c2 34 (hex) (if add=0) c2 25 34 c2 25 34 mx25u1635e 35 (hex) c2 35 (hex) (if add=0) c2 25 35 c2 25 35 mx25u3235e 36 (hex) c2 36 (hex) (if add=0) c2 25 36 c2 25 36
10 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 pin configurations pin description 8-land uson (4x4mm) 8-pin sop (150mil) / 8-pin sop (200mil) symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) sclk clock input wp#/sio2 write protection: connect to gnd or serial data input & output (for 4xi/o read mode) sio3 serial data input & output (for 4xi/o read mode) vcc + 1.8v power supply gnd ground 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc sio3 sclk si/sio0 8 7 6 5 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc sio3 sclk si/sio0 8-land wson (6x5mm) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc sio3 sclk si/sio0
11 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# wp#/sio2 sio3
12 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 data protection the mx25u8035e/mx25u1635e/mx25u3235e is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specifc command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. ? power-on reset and tpuw: to avoid sudden power switch by system power supply transition, the power-on reset and tpuw (internal timer) may protect the flash. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - write status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase 32kb (be32k) command completion - block erase (be) command completion - chip erase (ce) command completion - program/erase suspend - softreset command completion - write security register (wrscur) command completion - write protection selection (wpsel) command completion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res) and softreset command. ? advanced security features: there are some protection and security features which protect content from inadvertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area defnition is shown as table of "protected area sizes", the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of "protected area sizes". - the hardware proteced mode (hpm) use wp#/sio2 to protect the (bp3, bp2, bp1, bp0) bits and status register write protect bit. - in four i/o and qpi mode, the feature of hpm will be disabled.
13 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting device unique serial number - which may be set by factory or system customer. please refer to table 3: 4k-bit secured otp defnition. - security register bit 0 indicates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enter security otp (enso) command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exit security otp (exso) command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table. 8 of "security register defnition" for security register bit defnition and table.3 of "4k-bit secured otp defnition" for address range defnition. - note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 4k-bit secured otp mode, array access is not allowed. table 3. 4k-bit secured otp defnition table 2. protected area sizes status bit protect level bp3 bp2 bp1 bp0 8mb 16mb 32mb 0 0 0 0 0 (none) 0 (none) 0 (none) 0 0 0 1 1 (1block, protected block 15th) 1 (1block, protected block 31st) 1 (1block, protected block 63rd) 0 0 1 0 2 ( 2 b l o c k s , p r o t e c t e d b l o c k 14th~15th) 2 ( 2 b l o c k s , p r o t e c t e d b l o c k 30th~31st) 2 ( 2 b l o c k s , p r o t e c t e d b l o c k 62nd~63rd) 0 0 1 1 3 ( 4 b l o c k s , p r o t e c t e d b l o c k 12th~15th) 3 ( 4 b l o c k s , p r o t e c t e d b l o c k 28th~31st) 3 ( 4 b l o c k s , p r o t e c t e d b l o c k 60th~63rd) 0 1 0 0 4 ( 8 b l o c k s , p r o t e c t e d b l o c k 8th~15th) 4 ( 8 b l o c k s , p r o t e c t e d b l o c k 24th~31st) 4 (8blocks, protected block 56th- 63rd) 0 1 0 1 5 (16blocks, protected all) 5 (16blocks, protected block 16th~31st) 5 (16blocks, protected block 48th~63rd) 0 1 1 0 6 (16blocks, protected all) 6 (32blocks, protected all) 6 (32blocks, protected block 32nd~63rd) 0 1 1 1 7 (16blocks, protected all) 7 (32blocks, protected all) 7 (64blocks, protected all) 1 0 0 0 8 (16blocks, protected all) 8 (32blocks, protected all) 8 (64blocks, protected all) 1 0 0 1 9 (16blocks, protected all) 9 (32blocks, protected all) 9 (32blocks, protected block 0th~31st) 1 0 1 0 10 (16blocks, protected all) 10 (16blocks, protected block 0th~15th) 10 (48blocks, protected block 0th~47th) 1 0 1 1 11 (8blocks, protected block 0th~7th) 11 (24blocks, protected block 0th~23rd) 11 (56blocks, protected block 0th~55th) 1 1 0 0 12 (12blocks, protected block 0th~11th) 12 (28blocks, protected block 0th~27th) 12 (60blocks, protected block 0th~59th) 1 1 0 1 13 (14blocks, protected block 0th~13th) 13 (30blocks, protected block 0th~29th) 13 (62blocks, protected block 0th~61st) 1 1 1 0 14 (15blocks, protected block 0th~14th) 14 (31blocks, protected block 0th~30th) 14 (63blocks, protected block 0th~62nd) 1 1 1 1 15 (16blocks, protected all) 15 (32blocks, protected all) 15 (64blocks, protected all) address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a
14 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 table 4-1. memory organization (8mb) memory organization block (64kb) block (32kb) sector (4kb) address range 15 31 | 30 255 0ff000h 0fffffh : : : 240 0f0000h 0f0fffh 14 29 | 28 239 0ef000h 0effffh : : : 224 0e0000h 0e0fffh 13 27 | 26 223 0df000h 0dffffh : : : 208 0d0000h 0d0fffh 12 25 | 24 207 0cf000h 0cffffh : : : 192 0c0000h 0c0fffh 11 23 | 22 191 0bf000h 0bffffh : : : 176 0b0000h 0b0fffh 10 21 | 20 175 0af000h 0affffh : : : 160 0a0000h 0a0fffh 9 19 | 18 159 09f000h 09ffffh : : : 144 090000h 090fffh 8 17 | 16 143 08f000h 08ffffh : : : 128 080000h 080fffh 7 15 | 14 127 07f000h 07ffffh : : : 112 070000h 070fffh 6 13 | 12 111 06f000h 06ffffh : : : 96 060000h 060fffh 5 11 | 10 95 05f000h 05ffffh : : : 80 050000h 050fffh 4 9 | 8 79 04f000h 04ffffh : : : 64 040000h 040fffh 3 7 | 6 63 03f000h 03ffffh : : : 48 030000h 030fffh 2 5 | 4 47 02f000h 02ffffh : : : 32 020000h 020fffh 1 3 | 2 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 1 | 0 15 00f000h 00ffffh : : : 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh
15 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 table 4-2. memory organization (16mb) block (64kb) block (32kb) sector (4kb) address range 31 63 | 62 511 1ff000h 1fffffh : : : 496 1f0000h 1f0fffh 30 61 | 60 495 1ef000h 1effffh : : : 480 1e0000h 1e0fffh 29 59 | 58 479 1df000h 1dffffh : : : 464 1d0000h 1d0fffh 28 57 | 56 463 1cf000h 1cffffh : : : 448 1c0000h 1c0fffh 27 55 | 54 447 1bf000h 1bffffh : : : 432 1b0000h 1b0fffh 26 53 | 52 431 1af000h 1affffh : : : 416 1a0000h 1a0fffh 25 51 | 50 415 19f000h 19ffffh : : : 400 190000h 190fffh 24 49 | 48 399 18f000h 18ffffh : : : 384 180000h 180fffh 23 47 | 46 383 17f000h 17ffffh : : : 368 170000h 170fffh 22 45 | 44 367 16f000h 16ffffh : : : 352 160000h 160fffh 21 43 | 42 351 15f000h 15ffffh : : : 336 150000h 150fffh 20 41 | 40 335 14f000h 14ffffh : : : 320 140000h 140fffh 19 39 | 38 319 13f000h 13ffffh : : : 304 130000h 130fffh 18 37 | 36 303 12f000h 12ffffh : : : 288 120000h 120fffh 17 35 | 34 287 11f000h 11ffffh : : : 272 110000h 110fffh 16 33 | 32 271 10f000h 10ffffh : : : 256 100000h 100fffh block (64kb) block (32kb) sector (4kb) address range 15 31 | 30 255 0ff000h 0fffffh : : : 240 0f0000h 0f0fffh 14 29 | 28 239 0ef000h 0effffh : : : 224 0e0000h 0e0fffh 13 27 | 26 223 0df000h 0dffffh : : : 208 0d0000h 0d0fffh 12 25 | 24 207 0cf000h 0cffffh : : : 192 0c0000h 0c0fffh 11 23 | 22 191 0bf000h 0bffffh : : : 176 0b0000h 0b0fffh 10 21 | 20 175 0af000h 0affffh : : : 160 0a0000h 0a0fffh 9 19 | 18 159 09f000h 09ffffh : : : 144 090000h 090fffh 8 17 | 16 143 08f000h 08ffffh : : : 128 080000h 080fffh 7 15 | 14 127 07f000h 07ffffh : : : 112 070000h 070fffh 6 13 | 12 111 06f000h 06ffffh : : : 96 060000h 060fffh 5 11 | 10 95 05f000h 05ffffh : : : 80 050000h 050fffh 4 9 | 8 79 04f000h 04ffffh : : : 64 040000h 040fffh 3 7 | 6 63 03f000h 03ffffh : : : 48 030000h 030fffh 2 5 | 4 47 02f000h 02ffffh : : : 32 020000h 020fffh 1 3 | 2 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 1 | 0 15 00f000h 00ffffh : : : 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh
16 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 table 4-3. memory organization (32mb) block (64kb) block (32kb) sector (4kb) address range 63 127 | 126 1023 3ff000h 3fffffh : : : 1008 3f0000h 3f0fffh 62 125 | 124 1007 3ef000h 3effffh : : : 992 3e0000h 3e0fffh 61 123 | 122 991 3df000h 3dffffh : : : 976 3d0000h 3d0fffh 60 121 | 120 975 3cf000h 3cffffh : : : 960 3c0000h 3c0fffh 59 119 | 118 959 3bf000h 3bffffh : : : 944 3b0000h 3b0fffh 58 117 | 116 943 3af000h 3affffh : : : 928 3a0000h 3a0fffh 57 115 | 114 927 39f000h 39ffffh : : : 912 390000h 390fffh 56 113 | 112 911 38f000h 38ffffh : : : 896 380000h 380fffh 55 111 | 110 895 37f000h 37ffffh : : : 880 370000h 370fffh 54 109 | 108 879 36f000h 36ffffh : : : 864 360000h 360fffh 53 107 | 106 863 35f000h 35ffffh : : : 848 350000h 350fffh 52 105 | 104 847 34f000h 34ffffh : : : 832 340000h 340fffh 51 103 | 102 831 33f000h 33ffffh : : : 816 330000h 330fffh 50 101 | 100 815 32f000h 32ffffh : : : 800 320000h 320fffh 49 99 | 98 799 31f000h 31ffffh : : : 784 310000h 310fffh 48 97 | 96 783 30f000h 30ffffh : : : 768 300000h 300fffh block (64kb) block (32kb) sector (4kb) address range 47 95 | 94 767 2ff000h 2fffffh : : : 752 2f0000h 2f0fffh 46 93 | 92 751 2ef000h 2effffh : : : 736 2e0000h 2e0fffh 45 91 | 90 735 2df000h 2dffffh : : : 720 2d0000h 2d0fffh 44 89 | 88 719 2cf000h 2cffffh : : : 704 2c0000h 2c0fffh 43 87 | 86 703 2bf000h 2bffffh : : : 688 2b0000h 2b0fffh 42 85 | 84 687 2af000h 2affffh : : : 672 2a0000h 2a0fffh 41 83 | 82 671 29f000h 29ffffh : : : 656 290000h 290fffh 40 81 | 80 655 28f000h 28ffffh : : : 640 280000h 280fffh 39 79 | 78 639 27f000h 27ffffh : : : 624 270000h 270fffh 38 77 | 76 623 26f000h 26ffffh : : : 608 260000h 260fffh 37 75 | 74 607 25f000h 25ffffh : : : 592 250000h 250fffh 36 73 | 72 591 24f000h 24ffffh : : : 576 240000h 240fffh 35 71 | 70 575 23f000h 23ffffh : : : 560 230000h 230fffh 34 69 | 68 559 22f000h 22ffffh : : : 544 220000h 220fffh 33 67 | 66 543 21f000h 21ffffh : : : 528 210000h 210fffh 32 65 | 64 527 20f000h 20ffffh : : : 512 200000h 200fffh
17 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 block (64kb) block (32kb) sector (4kb) address range 31 63 | 62 511 1ff000h 1fffffh : : : 496 1f0000h 1f0fffh 30 61 | 60 495 1ef000h 1effffh : : : 480 1e0000h 1e0fffh 29 59 | 58 479 1df000h 1dffffh : : : 464 1d0000h 1d0fffh 28 57 | 56 463 1cf000h 1cffffh : : : 448 1c0000h 1c0fffh 27 55 | 54 447 1bf000h 1bffffh : : : 432 1b0000h 1b0fffh 26 53 | 52 431 1af000h 1affffh : : : 416 1a0000h 1a0fffh 25 51 | 50 415 19f000h 19ffffh : : : 400 190000h 190fffh 24 49 | 48 399 18f000h 18ffffh : : : 384 180000h 180fffh 23 47 | 46 383 17f000h 17ffffh : : : 368 170000h 170fffh 22 45 | 44 367 16f000h 16ffffh : : : 352 160000h 160fffh 21 43 | 42 351 15f000h 15ffffh : : : 336 150000h 150fffh 20 41 | 40 335 14f000h 14ffffh : : : 320 140000h 140fffh 19 39 | 38 319 13f000h 13ffffh : : : 304 130000h 130fffh 18 37 | 36 303 12f000h 12ffffh : : : 288 120000h 120fffh 17 35 | 34 287 11f000h 11ffffh : : : 272 110000h 110fffh 16 33 | 32 271 10f000h 10ffffh : : : 256 100000h 100fffh block (64kb) block (32kb) sector (4kb) address range 15 31 | 30 255 0ff000h 0fffffh : : : 240 0f0000h 0f0fffh 14 29 | 28 239 0ef000h 0effffh : : : 224 0e0000h 0e0fffh 13 27 | 26 223 0df000h 0dffffh : : : 208 0d0000h 0d0fffh 12 25 | 24 207 0cf000h 0cffffh : : : 192 0c0000h 0c0fffh 11 23 | 22 191 0bf000h 0bffffh : : : 176 0b0000h 0b0fffh 10 21 | 20 175 0af000h 0affffh : : : 160 0a0000h 0a0fffh 9 19 | 18 159 09f000h 09ffffh : : : 144 090000h 090fffh 8 17 | 16 143 08f000h 08ffffh : : : 128 080000h 080fffh 7 15 | 14 127 07f000h 07ffffh : : : 112 070000h 070fffh 6 13 | 12 111 06f000h 06ffffh : : : 96 060000h 060fffh 5 11 | 10 95 05f000h 05ffffh : : : 80 050000h 050fffh 4 9 | 8 79 04f000h 04ffffh : : : 64 040000h 040fffh 3 7 | 6 63 03f000h 03ffffh : : : 48 030000h 030fffh 2 5 | 4 47 02f000h 02ffffh : : : 32 020000h 020fffh 1 3 | 2 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 1 | 0 15 00f000h 00ffffh : : : 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh
18 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock (sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as figure 1. "serial modes supported". 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, 2read, 4read,res, rems, sqiid, rddmc, rdblock, the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be32k, be, ce, pp, 4pp, dp, enso, exso, wrscur, wpsel, sblk, sbulk, gbulk, suspend, resume, nop, rsten, rst, eqio, rstqio the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglected and not affect the current operation of write status register, program, erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb
19 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 quad peripheral interface (qpi) read mode qpi protocol enables user to take full advantage of quad i/o serial flash by providing the quad i/o interface in command cycles, address cycles and as well as data output cycles. enable qpi mode by issuing 35h command, the qpi mode is enable. figure 2. enable qpi sequence (command 35h) mode 3 sclk sio0 cs# mode 0 234567 35 sio[3:1] 0 1 quad peripheral interface (qpi) operation to use qpi protocol, the host drives cs# low then sends the fast read command, 0bh, followed by 6 address cycles and four dummy cycles. most signifcant bit (msb) comes frst, as shown in fgure 3. after the dummy cycle, the quad peripheral interface (qpi) flash memory outputs data on the falling edge of the sclk signal starting from the specifed address location. the device continually streams data output through all addresses until terminated by a low-to-high transition on cs#. the internal address pointer automatically increases until the highest memory address is reached. when reached the highest memory addrss, the address pointer returns to the beginning of the address space. sclk sio[3:0] cs# mode 3 mode 0 mode 0 msb data out data in 0b x x a5 a4 a3 a2 a1 a0 x x h0 l0 h1 l1 h2 l2 h3 l3 0 mode3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 figure 3. high-speed read sequence (qpi) (command 0bh)
20 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 reset qpi mode by issuing f5h command, the device is reset to 1-i/o spi mode. fast qpi read mode (fastrdq) to increase the code transmission speed, the device provides a "fast qpi read mode" (fastrdq). by issuing command code ebh, the fastrdq mode is enable. the number of dummy cycle increase from 4 to 6 cycles. the read cycle frequency will increase from 84mhz to 104mhz. figure 5. fast qpi read mode (fastrdq) (command ebh) 3 e d o m sclk sio[3:0] cs# mode 3 a5 a4 a3 a2 a1 a0 x x mode 0 mode 0 msb data out data in eb h0 l0 h1 l1 h2 l2 h3 l3 x x x x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 figure 4. reset qpi mode (command f5h) sclk sio[3:0] ce# f5
21 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 command description table 5. command set command (byte) wren* (write enable) wrdi * (write disable) rdsr * (read status register) wrsr * (write status register) 4pp (quad page program) se * (sector erase) be 32k * (block erase 32kb) be * (block erase 64kb) 1st byte 06 (hex) 04 (hex) 05 (hex) 01 (hex) 38 (hex) 20 (hex) 52 (hex) d8 (hex) 2nd byte values ad1 ad1 ad1 ad1 3rd byte ad2 ad2 ad2 ad2 4th byte ad3 ad3 ad3 ad3 action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to read out the values of the status register to write new values of the status register quad input to program the selected page to erase the selected sector to erase the selected 32k block to erase the selected block command (byte) ce * (chip erase) pp * (page program) dp * (deep power down) rdp * (release from deep power down) pgm/ers suspend * (suspends program/ erase) pgm/ers resume * (resumes program/ erase) 1st byte 60 or c7 (hex) 02 (hex) b9 (hex) ab (hex) b0 (hex) 30 (hex) 2nd byte ad1 3rd byte ad2 4th byte ad3 action to erase whole chip to program the selected page enters deep power down mode release from deep power down mode read commands i/o 1 1 2 4 4 4 4 read mode spi spi spi spi spi qpi qpi command (byte) read (normal read) fast read * (fast read data) 2read (2 x i/o read command) note1 w4read 4read * (4 x i/o read command) note1 fast read * (fast read data) 4read * (4 x i/o read command) note1 clock rate (mhz) 33 104 84 84 104 84 104 1st byte 03 (hex) 0b (hex) bb (hex) e7 (hex) eb (hex) 0b (hex) eb (hex) 2nd byte ad1(8) ad1(8) ad1(4) ad1(2) ad1(2) ad1(2) ad1(2) 3rd byte ad2(8) ad2(8) ad2(4) ad2(2) ad2(2) ad2(2) ad2(2) 4th byte ad3(8) ad3(8) ad3(4) ad3(2) ad3(2) ad3(2) ad3(2) 5th byte dummy(8) dummy(4) dummy(4) dummy(6) dummy(4) dummy(6) action n bytes read out until cs# goes high n bytes read out until cs# goes high n bytes read out by 2 x i/o until cs# goes high quad i/o read with 4 dummy cycles in 84mhz quad i/o read with 6 dummy cycles in 104mhz n bytes read out until cs# goes high quad i/o read with 6 dummy cycles in 104mhz program/erase commands
22 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 note 1: command set highlighted with (*) are supported both in spi and qpi mode. note 2: the count base is 4-bit for add(2) and dummy(2) because of 2 x i/o. and the msb is on si/sio1 which is different from 1 x i/o condition. note 3: add=00h will output the manufacturer id frst and add=01h will output device id frst. note 4: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hid - den mode. note 5: rst command only executed if rsten command is executed frst. any intervening command will disable reset. command (byte) rdid (read identifc- ation) rddmc * (read dmc) res * (read electronic id) rems (read electronic manufacturer & device id) enso * (enter secured otp) exso * (exit secured otp) rdscur * (read security register) 1st byte 9f (hex) 5a (hex) ab (hex) 90 (hex) b1 (hex) c1 (hex) 2b (hex) 2nd byte ad1 x x 3rd byte ad2 x x 4th byte ad3 x add (note 2) 5th byte spi (8 dummy) & qpi (2 dummy) action outputs jedec id: 1-byte manufact-urer id & 2-byte device id read dmc code to read out 1-byte device id output the manufacturer id & device id to enter the 4k-bit secured otp mode to exit the 4k- bit secured otp mode to read value of security register command (byte) wrscur * (write security register) sblk * (single block lock sbulk * (single block unlock) rdblock * (block protect read) gblk * (gang block lock) gbulk * (gang block unlock) nop * (no operation) 1st byte 2f (hex) 36 (hex) 39 (hex) 3c (hex) 7e (hex) 98 (hex) 00 (hex) 2nd byte ad1 ad1 ad1 3rd byte ad2 ad2 ad2 4th byte ad3 ad3 ad3 action to set the lock- down bit as "1" (once lock- down, cannot be update) individual block (64k- byte) or sector (4k-byte) write protect individual block (64k-byte) or sector (4k- byte) unprotect read individual block or sector write protect status whole chip write protect whole chip unprotect command (byte) rsten * (reset enable) rst * (reset memory) eqio (enable quad i/o) rstqio (reset quad i/ o) qpiid (qpi id read) sbl * (set burst length) wpsel * (write protect selection) 1st byte 66 (hex) 99 (hex) 35 (hex) f5 (hex) af (hex) c0 (hex) 68 (hex) 2nd byte value 3rd byte 4th byte action entering the qpi mode exiting the qpi mode id in qpi interface to set burst length to enter and enable individal block protect mode security/id/mode setting/reset commands
23 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, se, be32k, be, ce, and wrsr, which are intended to change the device content wel bit should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes lowsending wren instruction code cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care in spi mode. (please refer to figure 13- 1 and figure 13- 2) (2) write disable (wrdi) the write disable (wrdi) instruction is to reset write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsending wrdi instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care in spi mode. (please refer to figure 14- 1 and figure 14- 2) the wel bit is reset by following situations: - power-up - completion of write disable (wrdi) instruction - completion of write status register (wrsr) instruction - completion of page program (pp) instruction - completion of quad page program (4pp) instruction - completion of sector erase (se) instruction - completion of block erase 32kb (be32k) instruction - completion of block erase (be) instruction - completion of chip erase (ce) instruction - pgm/ers suspend (3) read identifcation (rdid) the rdid instruction is to read the manufacturer id of 1-byte and followed by device id of 2-byte. the mxic manufacturer id is c2(hex), the memory type id is 25(hex) as the frst-byte device id, and the individual device id of second-byte id are listed as table of "id defnitions". (please refer to table 7) the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code24-bits id data out on so to end rdid operation can drive cs# to high at any time during data out. while program/erase operation is in progress, it will not decode the rdid instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. (4) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress.
24 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 w ren c o mma n d program /erase c o mma n d write progra m data/address ( w rit e e r a se address) rdsr co mma n d read array data (sa m e addre ss o f pgm/ers) progra m /era s e s u cc essfully yes yes program /erase fail n o star t ver ify ok? w ip =0 ? progra m /e r a s e anoth e r blo c k ? pr og ra m /er a s e c o m p let e d n o yes n o rdsr co mma n d * yes w re n =1 ? n o * issue rdsr t o ch e ck bp[3:0]. * if wpsel = 1, issue rdslock to c h eck the block statu s . rdsr co mma n d read w el=0, b p[3:0] , q e, and srwd data the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. ( please refer to figure 16-1 and figure 16-2) for user to check if program/erase operation is fnished or not, rdsr instruction fow are shown as follows: program/ erase fow with read array data
25 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 program/ erase fow without read array data (read regpfail/regefail fag) w ren c o mma n d program /erase c o mma n d write progra m data/address ( w rit e e r a se address) rdsr co mma n d rdscur co mma n d program /era s e s u ccessfully yes n o program /erase fail yes star t regpfail/regefail =1 ? w ip =0 ? progra m /er a s e anoth e r blo c k ? progra m /era s e c o m p lete d n o yes n o rdsr co mma n d * yes w re n =1 ? n o * issue rdsr t o ch e ck bp[3:0]. * if wpsel = 1, issue rdslock to c h eck the block statu s . rdsr co mma n d read w el=0, b p[3:0] , q e, and srwd data
26 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 wrsr fow w ren c o mma n d w rsr co mma n d write status register d a t a rdsr co mma n d w rsr succ ess fully yes yes w rs r fa i l n o star t ver ify ok? w ip =0 ? n o rdsr co mma n d yes w re n =1 ? n o rdsr co mma n d read w el=0, b p[3:0] , q e, and srwd data
27 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 status register note 1: see the table 2 "protected area size". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored if it is applied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/erase/operations, wip bit needs to be confrm to be 0 before polling wel bit. after wip bit confrmed, wel bit needs to be confrm to be 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in table 2) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase 32kb (be32k), block erase (be) and chip erase (ce) instructions (only if block protect bits (bp3:bp0) set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default. which is un-protected. qe bit. the quad enable (qe) bit, non-volatile bit, performs spi quad modes when it is reset to "0" (factory default) to enable wp# or is set to "1" to enable quad sio2 and sio3. qe bit is only valid for spi mode. when operate in spi mode, and quad io read is desired (for command ebh/e7h, or quad io program, 38h). wrsr command has to be set the through status register bit 6, the qe bit. then the spi quad i/o commands (ebh/e7h/38h) will be accepted by fash. if qe bit is not set, spi quad i/o commands (ebh/e7h/38h) will be invalid commands, the device will not respond to them. once qe bit is set, all spi commands are valid. 1i/o commands and 2io commands can be issued no matter qe bit is "0" or "1". when in qpi mode, qe bit will not affect the operation of qpi mode at all. therefore either "0" or "1" value of qe bit does not affect the qpi mode operation. srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#/sio2) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. the srwd bit defaults to be "0".
28 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (5) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the protected area of memory (as shown in table 2 ). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on sics# goes high. (please refer to figure 17- 1 and figure 17- 2) the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 6. protection modes note: 1. as defned by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in table 2 . as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when srwd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm) note: if srwd bit=1 but wp#/sio2 is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase.
29 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 hardware protected mode (hpm): - when srwd bit=1, and then wp#/sio2 is low (or wp#/sio2 is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the wp#/sio2 to against data modifcation. note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0. if the system enter qpi or set qe=1, the feature of hpm will be disabled. (6) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes lowsending read instruction code 3-byte address on si data out on soto end read operation can use cs# to high at any time during data out. (please refer to figure 18) (7) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. read on spi mode the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si1-dummy byte (default) address on si data out on so to end fast_ read operation can use cs# to high at any time during data out. (please refer to figure 19- 1) read on qpi mode the sequence of issuing fast_read instruction in qpi mode is: cs# goes low sending fast_read instruction, 2 cycles 24-bit address interleave on sio3, sio2, sio1 & sio04 dummy cyclesdata out interleave on sio3, sio2, sio1 & sio0 to end qpi fast_read operation can use cs# to high at any time during data out. (please refer to figure 19- 2) in the performance-enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h,5ah,f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh,00h,aah or 55h and afterwards cs# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. (8) 2 x i/o read mode (2read) the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising
30 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maximum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address interleave on sio1 & sio0 4 dummy cycles on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out (please refer to figure 2 0 for 2 x i/o read mode timing waveform). while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. (9) 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x i/o read on spi mode (4read) the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 2+4 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. w4read instruction (e7) is also available is spi mode for 4 i/o read. the sequence is similar to 4read, but with only 4 dummy cycles. the clock rate runs at 84mhz. 4 x i/o read on qpi mode (4read) the 4read instruction also support on qpi command mode. the sequence of issuing 4read instruction qpi mode is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 2+4 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out (please refer to figure 2 1 for 4 x i/o read mode timing waveform). another sequence of issuing 4 read instruction especially useful in random access is : cs# goes low sending 4 read instruction 3-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles data out still cs# goes high cs# goes low (reduce 4 read instruction) 24-bit random access address (please refer to figure 22- 1 and figure 22- 2 for 4 x i/o read enhance performance mode timing waveform). in the performance-enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh,00h,aah or 55h and afterwards cs# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle.
31 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (10) burst read this device supports burst read in both spi and qpi mode. to set the burst length, following command operation is required issuing command: c0h in the frst byte (8-clocks), following 4 clocks defning wrap around enable with 0h and disable with1h. next 4 clocks is to defne wrap around depth. defnition as following table: the wrap around unit is defned within the 256byte page, with random initial address. its defned as wrap-around mode disable for the default state of the device. to exit wrap around, it is required to issue another c0 command in which data=1xh. otherwise, wrap around status will be retained until power down or reset command. to change wrap around depth, it is requried to issue another c0 command in which data=0xh. qpi 0bh ebh and spi ebh e7h support wrap around feature after wrap around enable. burst read is supported in both spi and qpi mode. the device id default without burst read. data wrap around wrap depth data wrap around wrap depth 1xh no x 00h yes 8-byte 1xh no x 01h yes 16-byte 1xh no x 02h yes 32-byte 1xh no x 03h yes 64-byte 0 cs# sclk sio 1 1 0 0 0 0 0 0 h h h h l l l l 1 2 3 4 6 7 8 9 10 1 12 13 14 15 5 spi mode qpi mode 0 cs# sclk sio[3:0] h0 msb lsb l0 c1 c0 1 2 3 note: msb=most signifcant bit lsb=least signifcant bit
32 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (11) performance enhance mode the device could waive the command cycle bits if the two cycle bits after address cycle toggles. (please note figure 22-1 and figure 22- 2. 4xi/o read enhance performance mode sequence) performance enhance mode is supported in both spi and qpi mode. in qpi mode, ebh 0bh and spi ebh e7h commands support enhance mode. the performance enhance mode is not supported in dual i/o mode. after entering enhance mode, following csb go high, the device will stay in the read mode and treat csb go low of the frst clock as address instead of command cycle. to exit enhance mode, a new fast read command whose frst two dummy cycles is not toggle then exit. or issue ffh command to exit enhance mode. (12) performance enhance mode reset (ffh) to conduct the performance enhance mode reset operation in spi mode, ffh command code, 8 clocks, should be issued in 1i/o sequence. in qpi mode, ffffffffh command code, 8 clocks, in 4i/o should be issued. (please refer to figure 34) if the system controller is being reset during operation, the fash device will return to the standard spi operation. upon reset of main chip, spi instruction would be issued from the system. instructions like read id (9fh) or fast read (0bh) would be issued. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to figure 34) (13) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table of memory organization) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to figure 25- 1 and figure 25- 2) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the sector is protected by bp3, bp2, bp1, bp0 bits, the sector eras e (se) instruction will not be executed on the sector.
33 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (14) block erase (be32k) the block erase (be32k) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 32k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be32k). any address of the block (see table of memory organization) is a valid address for block erase (be32k) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be32k instruction is: cs# goes low sending be32k instruction code 3-byte address on sics# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to figure 26- 1 and figure 26- 2) the self-timed block erase cycle time (tbe32k) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the block erase cycle is in progress. the wip sets 1 during the tbe32k timing, and sets 0 when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3, bp2, bp1, bp0 bits, the block erase (tbe32k) instruction will not be executed on the block. (15) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (please refer to table of memory organization) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to figure 27- 1 and figure 27- 2) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the block erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3, bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the block. (16) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes lowsending ce instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to figure 28- 1 and figure 28- 2) the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in
34 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3, bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp3, bp2, bp1, bp0 all set to "0". (17) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. if the entire 256 data bytes are going to be programmed, a7-a0 (the eight least signifcant address bits) should be set to 0. if the eight least signifcant address bits (a7-a0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address a7-a0 are all 0). if more than 256 bytes are sent to the device, the data of the last 256- byte is programmed at the request page and previous data will be disregarded. if less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. (please refer to figure 23- 1 and figure 23- 2) the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to figure 23) (18) 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" before sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 33mhz. for system with faster clock, the quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data fows in. therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 33mhz below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0]cs# goes high.
35 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (19) deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to entering the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when cs# goes high, it's only in deep power-down mode not standby mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (please refer to figure 29- 1 and figure 29- 2) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction and softreset command. (those instructions allow the id being reading out). when power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for dp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode. (20) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in table 1 0 . ac characteristics. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id defnitions on next page. this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. the sequence is shown as figure 30- 1, figure 30- 2, figure 31- 1 and figure 31- 2 . even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeatedly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power- down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction.
36 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 table 7. id defnitions command type mx25u8035e mx25u1635e rdid (jedec id) manufacturer id memory type memory density manufacturer id memory type memory density c2 25 34 c2 25 35 res electronic id electronic id 34 35 rems manufacturer id device id manufacturer id device id c2 34 c2 35 (21) read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for mxic (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in figure 3 2 . the device id values are listed in table 7 of id defnitions. if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. (22) qpi id read (qpiid) the qpiid read instruction identifes the devices as mx25u8035e/mx25u1635e/3235e and manufacturer as mxic. the sequence of issue qpiid instruction is cs# goes lowsending qpi id instructiondata out on socs# goes high. most signifcant bit (msb) frst. immediately following the command cycle the device outputs data on the falling edge of the sclk signal. the data output stream is continuous until terminated by a low-tohigh transition of cs#. the device outputs three bytes of data: manufacturer, device type, and device id. command type mx25u3235e rdid (jedec id) manufacturer id memory type memory density c2 25 36 res electronic id 36 rems manufacturer id device id c2 36
37 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (23) enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. the additional 4k-bit secured otp is independent from main array, which may use to store unique serial number for system identifer. after entering the secured otp mode, and then follow standard read or program, procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. please note that wrsr/wrscur commands are not acceptable during the access of secure otp region, once security otp is lock down, only read related commands are valid. (24) exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (25) read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously . the sequence of issuing rdscur instruction is : cs# goes lowsending rdscur instructionsecurity register data out on so cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the defnition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non-factory lock; "1" indicates factory-lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for customer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be update any more. while it is in 4k-bit secured otp mode, main array access is not allowed.
38 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (26) write security register (wrscur) the wrscur instruction is for changing the values of security register bits. the wren (write enable) instruction is required before issuing wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wpsel e_fail p_fail reserved erase suspend bit program suspend bit ldso (indicate if lock-down) secured otp indicator bit 0=normal wp mode 1=individual mode (default=0) 0=normal erase succeed 1=individual erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) - 0=erase is not suspended 1= erase suspended (default=0) 0=program is not suspended 1= program suspended (default=0) 0 = not lock- down 1 = lock-down (cannot program/ erase otp) 0 = non- factory lock 1 = factory lock non-volatile bit (otp) volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit (otp) non-volatile bit (otp) table 8. security register defnition (27) write protection selection (wpsel) when the system accepts and executes wpsel instruction, the bit 7 in security register will be set. the wren (write enable) instruction is required before issuing wpsel instruction. it will activate sblk, sbulk, rdblock, gblk, gbulk etc instructions to conduct block lock protection and replace the original software protect mode (spm) use (bp3~bp0) indicated block methods. the sequence of issuing wpsel instruction is: cs# goes low sending wpsel instruction to enter the individual block protect mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. every time after the system is powered-on, and the security register bit 7 is checked to be wpsel=1, all the blocks or sectors will be write protected by default. user may only unlock the blocks or sectors via sbulk and gbulk instruction. program or erase functions can only be operated after the unlock instruction is conducted. once wpsel is setted, it cannot be changed.
39 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 wpsel flow rdscur(2bh) command rdsr command rdscur(2bh) command wpsel set successfully yes yes wpsel set fail no start wpsel=1? wip=0? no wpsel disable, block protected by bp[3:0] yes no wren command wpsel=1? wpsel(68h) command wpsel enable. block protected by individual lock (sblk, sbulk, ? etc). wpsel instruction function fow is as follows:
40 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 block lock flow rdscur(2bh) command start wren command sblk command ( 36h + 24bit address ) rdsr command rdblock command ( 3ch + 24bit address ) block lock successfully yes yes block lock fail no data = ffh ? wip=0? lock another block? block lock completed no yes no no yes wpsel=1? wpsel command (28) single block lock/unlock protection (sblk/sbulk) these instructions are only effective after wpsel was executed. the sblk instruction is for write protection a specifed block (or sector) of memory, using a max -a16 or (a max -a12) address bits to assign a 64kbyte block (or 4k bytes sector) to be protected as read only. the sbulk instruction will cancel the block (or sector) write protection state. this feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (gbulk). the wren (write enable) instruction is required before issuing sblk/sbulk instruction. the sequence of issuing sblk/sbulk instruction is: cs# goes low send sblk/sbulk (36h/39h) instructionsend 3 address bytes assign one block (or sector) to be protected on si pin cs# goes high. the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. sblk/sbulk instruction function fow is as follows:
41 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 block unlock flow wren command rdscur(2bh) command sbulk command ( 39h + 24bit address ) rdsr command yes rdblock command to verify ( 3ch + 24bit address ) wip=0? unlock another block? yes no block unlock successfully no block unlock fail yes data = ff ? no yes unlock block completed? start wpsel=1? wpsel command
42 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (29) read block lock status (rdblock) this instruction is only effective after wpsel was executed. the rdblock instruction is for reading the status of protection lock of a specifed block (or sector), using a max -a16 (or a max -a12) address bits to assign a 64k bytes block (4k bytes sector) and read protection lock status bit which the frst byte of read-out cycle. the status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. the status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. the sequence of issuing rdblock instruction is: cs# goes low send rdblock (3ch) instruction send 3 address bytes to assign one block on si pin read block's protection lock status bit on so pin cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (30) gang block lock/unlock (gblk/gbulk) these instructions are only effective after wpsel was executed. the gblk/gbulk instruction is for enable/disable the lock protection block of the whole chip. the wren (write enable) instruction is required before issuing gblk/gbulk instruction. the sequence of issuing gblk/gbulk instruction is: cs# goes low send gblk/gbulk (7eh/98h) instruction cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the cs# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. (31) read dmc mode (rddmc) mx25u3235e/1635e/8035e features dmc mode. host system can retrieve the operating characteristics and vendor specifed information of this device by dmc mode. for more detail, please contact macronix. the rddmc (enter dmc) instruction is being issued as following: cs# low 5a opcode (query) dmc address (24-bit)dummy bitsdata out cs# high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (32) program/ erase suspend/ resume the device allow the interruption of sector-erase, block-erase or page-program operations and conduct other operations. details as follows. to enter the suspend/ resume mode: issuing b0h for suspend; 30h for resume (spi/qpi all acceptable) read security register bit2 (psb) and bit3 (esb) (please refer to table 9) to check suspend ready information. suspend to suspend ready timing: 20us. resume to another suspend timing: 1ms. esb bit (erase suspend bit) indicates the status of erase suspend operation. when issue a suspend command during erase operation esb=1, when erase operation resumes, esb will be reset to "0".
43 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (32-1) erase suspend erase suspend allow the interruption of all erase operations. after erase suspend, wel bit will be clear, only read related, resume and reset command can be accepted. (including: 03h, 0bh, bbh, ebh, e7h, 9fh, afh, 90h, 05h, 2bh, b1h, c1h, 5ah, 3ch, 30h, 66h, 99h, c0h, 35h, f5h, 00h, abh ) after issue erase suspend command, latency time 20us is needed before issue another command. for "suspend to read", "resume to read", "resume to suspend" timing specifcation please note figure 37- 1, figure 37- 2 and figure 37- 3. esb bit (erase suspend bit) indicates the status of erase suspend operation. when issue a suspend command during program operation esb=1, when erase operation resumes, esb will be reset to "0". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. when esb bit is issued, the write enable latch (wel) bit will be reset. see figure 37- 1 for suspend to read latency. (32-2) program suspend program suspend allows the interruption of all program operations. after program suspend, wel bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0bh, bbh, ebh, e7h, 9fh, afh, 90h, 05h, 2bh, b1h, c1h, 5ah, 3ch, 30h, 66h, 99h, c0h, 35h, f5h, 00h, abh ) after issue program suspend command, latency time 20us is needed before issue another command. for "suspend to read", "resume to read", "resume to suspend" timing specifcation please note figure 37- 1, figure 37- 2 and figure 37- 3. psb bit (program suspend bit) indicates the status of program suspend operation. when issue a suspend command during program operation psb=1, when program operation resumes, psb will be reset to "0". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode.
44 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (33) write-resume the write operation is being resumed when write-resume instruction issued. esb or psb (suspend status bit) in status register will be changed back to 0 the operation of write-resume is as follows: cs# drives low send write resume command cycle (30h) drive cs# high. by polling busy bit in status register, the internal write operation status could be checked to be completed or not. the user may also wait the time lag of tse, tbe, tpp for sector-erase, block-erase or page-programming. wren (command "06" is not required to issue before resume. resume to another suspend operation requires latency time of 1ms. when erase suspend is being resumed, the wel bit need to be set again if user desire to conduct the program or erase operation. please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resume. to restart the write command, disable the "performance enhance mode" is required. after the "performance enhance mode" is disable, the write-resume command is effective. (34) no operation (nop) the no operation command only cancels a reset enable command. nop has no impact on any other command. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. (35) software reset (reset-enable (rsten) and reset (rst)) the reset operation is used as a system (software) reset that puts the device in normal operating ready mode. this operation consists of two commands: reset-enable (rsten) and reset (rst). to reset the mx25u8035e/mx25u1635e/mx25u3235e the host drives cs# low, sends the reset-enable command (66h), and drives cs# high. next, the host drives cs# low again, sends the reset command (99h), and drives cs# high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. the reset operation requires the reset-enable command followed by the reset command. any command other than the reset command after the reset-enable command will disable the reset-enable. a successful command execution will reset the device to spi stand-by read mode, which are their respective default states, see figure 38. a device reset during an active program or erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. depending on the prior operation, the reset timing may vary. recovery from a write operation requires more latency time than recovery from other operations.
45 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 (36) reset quad i/o (rstqio) the reset quad i/o instruction, f5h, resets the device to 1-bit spi protocol operation. to execute a reset quad i/ o operation, the host drives cs# low, sends the reset quad i/o command cycle (f5h) then, drives cs# high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. note: for eqio/rstqio/c0 pcsb high width has to follow "write spec" tshsl as 30ns for next instruction.
46 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 power-on state the device is at below states when power-up: - standby mode (please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. when vcc is lower than vwi (por threshold voltage value), the internal logic is reset and the fash device has no response to any command. for further protection on the device, after vcc reaching the vwi level, a tpuw time delay is required before the device is fully accessible for commands like write enable (wren), page program (pp), quad page program (4pp), sector erase (se), block erase 32kb (be32k), block erase (be), chip erase (ce), wrscur and write status register (wrsr). if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - tpuw after vcc reached vwi level - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl, even time of tpuw has not passed. please refer to the fgure of "power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uf) - at power-down stage, the vcc drops below vwi level, all operations are disable and device has no response to any command. the data corruption might occur during the stage while a write, program, erase cycle is in progress.
47 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+1.0v or -0.5v for period up to 20ns. 4. all input and output pins may overshoot to vcc+0.2v. absolute maximum ratings electrical specifications capacitance ta = 25c, f = 1.0 mhz figure 6. maximum negative overshoot waveform figure 7. maximum positive overshoot waveform rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to vcc+0.5v 0v -0.5v 20ns vcc+1.0v 2.0v 20ns symbol parameter min. typ max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v
48 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 8. input test waveforms and measurement level figure 9. output loading ac measurement level input timing referance level output timing referance level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test cl 25k ohm 25k ohm +1.8v cl=30pf including jig capacitance
49 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 table 9. dc characteristics (temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v) notes : 1. typical values at vcc = 1.8v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vin = vcc or gnd isb1 vcc standby current 1 30 100 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 5 20 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 20 ma f=104mhz, (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 15 ma f=84mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 20 25 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 20 ma program status register in progress, cs#=vcc icc4 vcc sector/block (32k, 64k) erase current (se/be/be32k) 1 20 25 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 20 25 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.2vcc v vih input high voltage 0.8vcc vcc+0.4 v vol output low voltage 0.2 v iol = 100ua voh output high voltage vcc-0.2 v ioh = -100ua
50 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 table 10. ac characteristics (temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v) symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, pp, se, be, ce, dp, res,rdp wren, wrdi, rdid, rdsr, wrsr d.c. 104 mhz frsclk fr clock frequency for read instructions 33 mhz ftsclk ft clock frequency for 2read instructions 84 mhz fq clock frequency for 4read instructions (5) 84/104 mhz tch(1) tclh clock high time serial (fsclk) 4.5 ns 4pp and normal read (frsclk) 15 ns tcl(1) tcll clock low time serial (fsclk) 4.5 ns 4pp and normal read (frsclk) 15 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 7 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 7 ns tshsl(3) tcsh cs# deselect time read 12 ns write/erase/program 30 ns tshqz(2) tdis output disable time 8 ns tclqv tv clock low to output valid loading: 30pf/15pf loading: 30pf 8 ns loading: 15pf 6 ns tclqx tho output hold time 0 ns twhsl write protect setup time 20 ns tshwl write protect hold time 100 ns tdp(2) cs# high to deep power-down mode 10 us tres1(2) cs# high to standby mode without electronic signature read 10 us tres2(2) cs# high to standby mode with electronic signature read 10 us trcr recovery time from read 20 us trcp recovery time from program 20 us trce recovery time from erase 12 ms tw write status register cycle time 40 ms tbp byte-program 8 30 us tpp page program cycle time 1.2 3 ms tse sector erase cycle time 60 200 ms tbe32 block erase (32kb) cycle time 250 1000 ms tbe block erase (64kb) cycle time 500 2000 ms tce chip erase cycle time 8mb 5 10 s 16mb 9 20 s 32mb 18 40 s notes: 1. tch + tcl must be greater than or equal to 1/ frequency. 2. value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a wrsr instruction when sr wd is set at 1. 4. test condition is shown as figure 8,9. 5. when dummy cycle=4 (in both qpi & spi mode), clock rate=84mhz; when dummy cycle=6 (in both qpi & spi mode), clock rate=104mhz.
51 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 10. serial input timing timing analysis figure 11. output timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si
52 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 12. wp# setup timing and hold timing during wrsr when srwd=1 high-z 01h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so figure 13-1. write enable (wren) sequence (command 06) (spi mode) 2 1 34567 high-z 0 06h command sclk si cs# so figure 13-2. write enable (wren) sequence (command 06) (qpi mode) sclk sio[3:0] cs# 06h 0 1 command
53 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 14-1. write disable (wrdi) sequence (command 04) (spi mode) 2 1 34567 high-z 0 04h command sclk si cs# so figure 14-2. write disable (wrdi) sequence (command 04) (qpi mode) sclk sio[3:0] cs# 04h 0 1 command figure 15. read identifcation (rdid) sequence (command 9f) (spi mode only) 2 1 3456789 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9fh
54 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 16-1. read status register (rdsr) sequence (command 05) (spi mode) 2 1 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05h figure 16-2. read status register (rdsr) sequence (command 05) (qpi mode) 0 1 3 sclk s i o[3:0 ] cs# 05h 2 h0 l0 msb ls b 4 5 7 h0 l0 6 h0 l0 8 n h1 l1 st a tus byt e statu s byt e status byt e status byt e figure 17-1. write status register (wrsr) sequence (command 01) (spi mode) 2 1 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01h high-z command note : also supported in qpi mode with command and subsequent input/output in quad i/o mode.
55 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 18. read data bytes (read) sequence (command 03) (spi mode only) (33mhz) sclk si cs# so 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03h high-z command figure 17-2. write status register (wrsr) sequence (command 01) (qpi mode) sclk sio0 cs# c4, c0 sio1 c5, c1 5 4 0 1 2 3 sio2 c6, c2 6 sio3 c7, c3 command status 7 register in
56 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 19-1. read at higher speed (fast_read) sequence (command 0b) (spi mode) (104mhz) 23 2 1 3456789 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 configurable dummy cycle msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so 0bh command figure 19-2. read at higher speed (fast_read) sequence (command 0b) (qpi mode) (84mhz) sclk sio(3:0) cs# a5 a4 a3 a2 a1 a0 x x mode 0 msb lsb msb lsb data out 1 data out 2 data in 0bh x x h0 l0 h1 l1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3 e d o m 24 bit address command
57 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 20. 2 x i/o read mode sequence (command bb) (spi mode only) (84mhz) figure 21. 4 x i/o read mode sequence (command eb) (spi mode) (104mhz) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 10 11 18 19 20 bbh address bit22, bit20, bit18...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... address bit23, bit21, bit19...bit1 21 22 23 24 25 26 27 8 bit instruction 12 bit address 4 dummy cycle data output high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 12 10 11 13 14 ebh address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output note: 1. also supported in qpi mode with command and subsequent input/output in quad i/o mode and runs at 104mhz. 2. hi-impedance is inhibited for the two clock cycles. 3. p7p3, p6p2, p5p1 & p4p0 (toggling) is inhibited.
58 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 22-1. 4 x i/o read enhance performance mode sequence (command eb) (spi mode) (104mhz) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 12 10 11 13 14 ebh address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output sclk si/sio0 so/sio1 cs# address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 6 address cycles 4 dummy cycles performance enhance indicator (note) data output note: performance enhance mode, if p7p3 & p6p2 & p5p1 & p4p0 (toggling), ex: a5, 5a, 0f, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff
59 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 22-2. 4 x i/o read enhance performance mode sequence (command eb) (qpi mode) (104mhz) sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 mode 0 data out data in ebh x p(7:4) p(3:0) x x x h0 l0 h1 l1 4 dummy cycles performance enhance indicator sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 mode 0 data out msb lsb msb lsb msb lsb msb lsb 6 address cycles x p(7:4) p(3:0) x x x h0 l0 h1 l1 4 dummy cycles performance enhance indicator n+1 ............. 3 e d o m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 figure 23-1. page program (pp) sequence (command 02) (spi mode) 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02h command
60 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 24. 4 x i/o page program (4pp) sequence (command 38) (spi mode only) 20 21 17 16 12 8 4 0 13 9 5 1 4 4 4 4 0 0 0 0 5 5 5 5 1 1 1 1 2 1 3456789 6 address cycle data byte 1 data byte 2 data byte 3 data byte 4 0 22 18 14 10 6 2 23 19 15 11 7 3 6 6 6 6 2 2 2 2 7 7 7 7 3 3 3 3 sclk cs# si/sio0 so/sio1 nc/sio3 wp#/sio2 38h command 10 11 12 13 14 15 16 17 18 19 20 21 figure 23-2. page program (pp) sequence (command 02) (qpi mode) 2 1 0 3 e d o m sclk sio[3:0] cs# mode 0 data byte 2 data in 02h a5 a4 a3 a2 a1 a0 h0 l0 h1 l1 h2 l2 h3 l3 h255 l255 data byte 1 data byte 3 data byte 4 data byte 256 24 bit address command
61 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 25-1. sector erase (se) sequence (command 20) (spi mode) 24 bit address 2 1 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20h command figure 25-2. sector erase (se) sequence (command 20) (qpi mode) sclk sio[3:0] cs# 20h 2 3 5 7 1 0 a5 a4 msb lsb 4 a3 a2 6 a1 a0 24 bit address command figure 26-1. block erase 32kb (be32k) sequence (command 52) (spi mode) 24 bit address 2 1 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52h command figure 26-2. block erase 32kb (be32k) sequence (command 52) (qpi mode) sclk sio[3:0] cs# 52h 2 3 5 7 1 0 a5 a4 msb 4 a3 a2 6 a1 a0 24 bit address command
62 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 27-1. block erase (be) sequence (command d8) (spi mode) 24 bit address 2 1 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8h command figure 27-2. block erase (be) sequence (command d8) (qpi mode) sclk sio[3:0] cs# d8h 2 3 1 0 a5 a4 ms b 4 5 a3 a2 6 7 a1 a0 24 bit address command figure 28-1. chip erase (ce) sequence (command 60 or c7) (spi mode) 2 1 34567 0 60h or c7h sclk si cs# command figure 28-2. chip erase (ce) sequence (command 60 or c7) (qpi mode) sclk sio[3:0] cs# 60h or c7h 0 1 command
63 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 29-1. deep power-down (dp) sequence (command b9) (spi mode) 2 1 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9h command figure 29-2. deep power-down (dp) sequence (command b9) (qpi mode) sclk sio[3:0] cs# b9h 0 1 t dp deep power-down mode stand-by mode command figure 30-1. release from deep power-down and read electronic signature (res) sequence (command ab) (spi mode) 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 765432 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so abh command
64 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 31-1. release from deep power-down (rdp) sequence (command ab) (spi mode) 2 1 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so abh command figure 30-2. release from deep power-down and read electronic signature (res) sequence (command ab) (qpi mode) sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 mode 0 mode 3 msb lsb data out data in h0 l0 deep power-down mode stand-by mode 0 abh 1 2 3 4 6 7 5 24 bit address command figure 31-2. release from deep power-down (rdp) sequence (command ab) (qpi mode) sclk sio[3:0] cs# abh 0 1 t res1 deep power-down mode stand-by mode command
65 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. (2) instruction is either 90(hex). figure 32. read electronic manufacturer & device id (rems) sequence (command 90) (spi mode only) 15 14 13 3 2 1 0 2 1 3456789 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 765432 0 1 35 31 30 29 28 sclk si cs# so sclk si cs# so 90h high-z command
66 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 33. word read quad i/o instruction sequence (initial word read quad i/o instruction or previous p4=1) (spi mode only) (84mhz) 2 1 3456789 10 11 12 13 14 15 instruction (e7h) mode 3 mode 16 17 4 0 0 18 20 21 22 23 19 sclk io0 cs# 4 4 0 4 0 4 0 4 4 io switches from input to output 0 5 1 1 io1 5 5 1 5 1 5 1 5 5 1 6 2 2 io2 6 6 2 6 2 6 2 6 6 2 7 3 3 io3 7 a23-16 a15-8 a7-0 dummy byte 1 byte 2 byte 3 7 3 7 3 7 3 7 7 3 figure 34. performance enhance mode reset for fast read quad i/o (spi and qpi mode) 2 1 34567 mode 3 don?t care (spi) ffffffffh (qpi) don?t care (spi) ffffffffh (qpi) don?t care (spi) ffffffffh (qpi) mode mode 3 mode sclk io0 cs# io1 ffh (spi) ffffffffh (qpi) io2 io3 mode bit reset for quad i/o
67 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 35-1. reset sequence (spi mode) cs# sclk sio0 66h mode 3 mode 0 mode 3 mode 0 99h command command figure 35-2. reset sequence (qpi mode) mode 3 sclk sio[3:0] cs# mode 3 99h 66h mode 0 mode 3 mode 0 mode 0 t ceh command command figure 36. enable quad i/o sequence mode 3 0 1 sclk sio0 cs# mode 0 234567 35h sio[3:1]
68 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 37-1. suspend to read latency cs# program latency : 20us erase latency:20us suspend command [b0] read command figure 37-2. resume to read latency cs# tse/tbe/tpp resume command [30] read command figure 37-3. resume to suspend latency cs# 1ms resume command [30] suspend command [b0] figure 38. software reset recovery cs# mode 66 99 stand-by mode trcr trcp trce trcr: 20us (recovery time from read) trcp: 20us (recovery time from program) trce: 12ms (recovery time from erase)
69 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 39. power-up timing note: vcc (max.) is 2.0v and vcc (min.) is 1.65v. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: 1. these parameters are characterized only. table 11. power-up timing and vwi threshold v cc v cc (min) v wi reset state of the flash chip selection is not allowed program, erase and write commands are ignored tvsl tpuw time read command is allowed device is fully accessible v cc (max) symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low (vcc rise time) 300 us tpuw(1) time delay to write instruction 1 10 ms vwi(1) command inhibit voltage 1.0 1.4 v
70 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 operating conditions at device power-up and power-down ac timing illustrated in figure 40 and figure 41 are for the supply voltages and the control signals at device power- up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 40. ac timing at device power-up notes : 1. sampled, not 100% tested. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "ac characteristics" table. sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v
71 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 figure 41. power-down sequence c s # sclk v c c during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation.
72 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 erase and programming performance note: 1. typical program and erase time assumes the following conditions: 25 c, 1.8v, and checker board pattern. 2. under worst conditions of 85 c and 1.65v. 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming command. 4. the maximum chip programming time is evaluated under the worst conditions of 0c, vcc=1.8v, and 100k cycle with 90% confdence level. latch-up characteristics parameter min. typ. (1) max. (2) unit write status register cycle time 40 ms sector erase cycle time (4kb) 60 200 ms block erase cycle time (32kb) 250 1000 ms block erase cycle time (64kb) 500 2000 ms chip erase cycle time 8m 5 10 s 16m 9 20 s 32m 18 40 s byte program time (via page program command) 8 30 us page program time 0.9 3 ms erase/program cycle 100,000 cycles min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 1.8v, one pin at a time.
73 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 * advanced information ordering information part no. clock (mhz) operating current typ. (ma) standby current typ. (ua) temperature package remark mx25u8035em1i-10g* 104 45 5 -40 c~85 c 8-sop (150mil) pb-free mx25u8035em2i-10g* 104 45 5 -40 c~85 c 8-sop (200mil) pb-free MX25U8035EZUI-10G* 104 45 5 -40 c~85 c 8-uson (4x4mm) pb-free mx25u8035ezni-10g* 104 45 5 -40 c~85 c 8-wson (6x5mm) pb-free mx25u1635em1i-10g* 104 45 5 -40 c~85 c 8-sop (150mil) pb-free mx25u1635em2i-10g* 104 45 5 -40 c~85 c 8-sop (200mil) pb-free mx25u1635ezui-10g* 104 45 5 -40 c~85 c 8-uson (4x4mm) pb-free mx25u1635ezni-10g* 104 45 5 -40 c~85 c 8-wson (6x5mm) pb-free mx25u3235em2i-10g 104 45 5 -40 c~85 c 8-sop (200mil) pb-free mx25u3235ezni-10g 104 45 5 -40 c~85 c 8-wson (6x5mm) pb-free
74 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 part name description mx 25 u 10 m1 i g option: g: pb-free speed: 10: 104mhz temperature range: i: industrial (-40c to 85c) package: m1: 150mil 8-sop m2: 200mil 8-sop zu: uson zn: wson density & mode: 8035e: 8mb 1635e: 16mb 3235e: 32mb type: u: 1.8v device: 25: serial flash 1635e
75 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 package information
76 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010
77 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010
78 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010
79 mx25u8035e mx25u1635e mx25u3235e p/n: pm1472 rev. 1.0, apr. 01, 2010 revision history revision no. description page date 0.01 1. added mxsmio tm logo and 4 i/o 104mhz specifcations p6 jul/24/2009 2. take out 8wson and 200mil 8-sop package outline p9 3. added software reset p11 4. corrected supporting instructions p16 5. modifed dummy cycle numbers (from 2 to 4) p17 6. added qpi, write suspend/resume commands p19 7. added qpi operations in the command descriptions all 8. ac/dc modifcations; write suspend features modify p6,38,39,45 9. updated spi & qpi commands & descriptions all 10. remove loading relevance to clock rate p6 11. modify 32mb wson package as uson package p7 12. add wip, wel polling sequence description p22 13. add description about performance enhance mode not supported p27 in 2-i/o mode 14. add 104mhz note in ftsclk p45 15. added 8-sop 200mil package for 16mb; modifed 32mb from p7 uson to wson 16. added 8wson package information p9 17. added rdsr fow charts p22~24 18. change cfird command from a5 to 5a p19,40,41 19. modifed epn for package information correction and speed grade p70,71 (from -12g to -10g) 20. modifed erase/program time spec p6,48,69 21. added program/erase fow description p22,23 22. modifed performance enhance mode toggling description p56 23. revised fast program time and byte program time p6 24. added wrscur and wpsel in wel reset situation p11 25. modifed recovery time from read p48,66 dec/24/2009 0.02 1. modifed " qe bit" description p25 2. modifed four i/o and qpi mode description p11,20 3. modifed release read enable description p19,28 4. changed title from "advanced information" to "preliminary" p6 5. added mx25u8035e and mx25u8035e function all 0.03 1. revised tce p50,71 jan/27/2009 2. deleted trehz p50 1.0 1. removed "preliminary" p6 apr/01/2010 2. low power consumption: modifed current description p6,49 3. table 10. ac characteristics: modifed min. tslch/tchsh p50 4. modifed figure 40 p70 5. added figure 41 p71 6. modifed general description p8 7. modifed fast erase time p6 8. modifed page program cycle time from 0.9ms to 1.2ms p6,50 9. modifed "read dmc mode (rddmc)" description p42 10. changed the naming "cfi mode" as "dmc mode" p18,22,42 11. added dummy description p22 12. modifed fgure 38 p68
80 m acronix i nternational c o., l td. macronix offces : taiwan headquarters, fab2 macronix, international co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 taipei offce macronix, international co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix offces : china macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 macronix (hong kong) co., limited, suzhou offce no.5, xinghai rd, suzhou industrial park, suzhou china 215021 tel: +86-512-62580888 ext: 3300 fax: +86-512-62586799 macronix (hong kong) co., limited, shenzhen offce room 1401 & 1404, block a, tianan hi-tech plaza tower, che gong miao, futiandistrict, shenzhen prc 518040 tel: +86-755-83433579 fax: +86-755-83438078 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice. macronix offces : japan macronix asia limited. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix offces : korea macronix asia limited. #906, 9f, kangnam bldg., 1321-4, seocho-dong, seocho-ku, 135-070, seoul, korea tel: +82-02-588-6887 fax: +82-02-588-6828 macronix offces : singapore macronix pte. ltd. 1 marine parade central, #11-03 parkway centre, singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix offces : europe macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 macronix offces : usa macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. copyright? macronix international co., ltd. 2009~2010. all rights reserved. macronix, mxic, mxic logo, mx logo, mxsmio , are trademarks or registered trademarks of macronix international co., ltd.. the names and brands of other companies are for identifcation purposes only and may be claimed as the property of the respective companies. mx25u8035e mx25u1635e mx25u3235e

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